High Bandwidth Flash
A NAND-flash-based memory concept positioned for high-capacity AI inference, where model weights and retrieval-heavy workloads can strain HBM capacity.
Independent technical tracker · Updated July 7, 2026
High Bandwidth Flash (HBF) Tracker
HBF is the emerging flash-memory idea aimed at the AI inference memory wall: far more capacity than DRAM-based HBM, with packaging and standardization work intended to bring NAND closer to accelerator-class bandwidth.
- Event window
- FMS26 · Aug 4-6, 2026
- Primary workload
- AI inference capacity tier
- Tracker posture
- Independent, source-linked
Fast read
HBF is a capacity-first answer to accelerator memory pressure.
The short version: HBF is not just a faster SSD, and it is not a drop-in synonym for HBM. It is a proposed high-bandwidth, high-capacity flash-memory tier whose success depends on packaging, controller architecture, standardization, and software adoption.
Terminology
The HBF vocabulary, without the pitch deck fog.
HBM
High Bandwidth Memory is stacked DRAM used beside accelerators. It remains the latency and bandwidth reference point, especially for training-class systems.
3D NAND and CBA
HBF messaging points to 3D NAND density and CMOS-bonded-array manufacturing as a path to higher bit density than DRAM stacks.
OCP standardization
Open Compute Project discussions matter because HBF needs a usable ecosystem: package definitions, interfaces, controller behavior, and procurement confidence.
Inference memory wall
The bottleneck that appears when serving larger models demands more local, fast-access memory than practical HBM capacity can economically provide.
What HBF is not
It is not confirmed as a universal HBM replacement, not a JEDEC-style finished product spec today, and not the same thing as commodity SSD flash.
Gen1-Gen3 roadmap
A practical tracker for what each generation needs to prove.
Public HBF roadmaps describe a capacity and bandwidth scaling arc. Until vendors publish stable product specifications, the most useful lens is what each generation must validate for real accelerator deployments.
Gen 1
Definition
Prove the package
Establish the physical memory stack, controller path, accelerator attachment model, and realistic inference workloads where capacity offsets flash latency.
- Baseline HBF module architecture
- Reference performance claims
- Early ecosystem demonstrations
Gen 2
Scale
Increase density and efficiency
Move beyond first demonstrations with higher capacity, improved bandwidth per package, lower energy per bit moved, and clearer procurement language.
- Interface and form-factor maturity
- Controller/software integration
- Datacenter qualification path
Gen 3
Adoption
Become a deployable tier
The decisive question is whether HBF becomes a standard AI memory tier that buyers can compare against HBM, CXL memory, LPDDR stacks, and SSD offload.
- Repeatable supplier ecosystem
- Framework-aware memory hierarchy
- Clear cost-per-token economics
FMS26 countdown
Tracking the run-up to FMS: the Future of Memory and Storage.
FMS26 is scheduled for August 4-6, 2026 at the Santa Clara Convention Center. This countdown targets the morning of opening day in Pacific time.
Official FMS event site
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News brief
What changed in the HBF conversation.
Short summaries are intentionally source-linked and conservative. HBF is still an emerging category, so claims here are tracked as public positioning unless marked as confirmed product specifications.
SanDisk framed HBF as memory-centric AI infrastructure.
SanDisk's technical messaging connects HBF to BiCS 3D NAND, CMOS-bonded-array manufacturing, and the need for much larger local memory capacity in AI systems.
Read the SanDisk explainerSanDisk and SK hynix pushed HBF toward standardization.
Coverage from FMS reported that the companies were working through OCP to define HBF as an open, NAND-based alternative for AI inference memory capacity.
Read the FMS coverageCompeting AI memory approaches are moving quickly.
Qualcomm's High Bandwidth Compute concept shows why HBF will be evaluated against multiple memory architectures, not just against today's HBM supply chain.
Read the market contextSources and update policy
This page is an independent editorial tracker. It is not affiliated with FMS, SanDisk, SK hynix, OCP, Qualcomm, or any standards body. Source links are included to make the page useful and auditable during the FMS26 search cycle.